1. Field of the Invention
The invention relates generally to the semiconductor power devices. More particularly, this invention relates to an inverted grounded source lateral diffusion metal oxide semiconductor field effect transistor (LDMOSFET) structure and manufacturing method.
2. Description of the Prior Art
Conventional technologies to further reduce the source inductance for semiconductor power devices including the source inductance in FET, MOSFET and JFET devices are challenged by several technical difficulties and limitations. Specifically, there are technical challenges faced by those of ordinary skill in the art to reduce the source inductance. Meanwhile, there are ever increasing demand to reduce the source inductance in the semiconductor power devices because more and more power devices are required for applications that demand these devices to function with high efficiency, high gain, and high frequency. Generally, reduction of source inductance can be achieved by eliminating the bond-wires in the package of a semiconductor power device. Many attempts are made to eliminate the bond-wires by configuring the semiconductor substrate as a source electrode for connection of the semiconductor power devices. There are difficulties in such approaches due to the facts that typical vertical semiconductor power devices is arranged to place the drain electrode on the substrate. The vertical power devices, either as trenched gate or planar gate DMOS devices, use the substrate as the drain electrode with the current flowing vertically from the source region disposed at the top of the substrate down to the drain region disposed at the bottom of the substrate and the top source electrode usually requires bond wires for electrical connections during a device packaging process thus increasing the source inductance.
Several lateral DMOS with bottom source have been disclosed as prior art. A lateral DMOS device typically includes a deep P+ sinker region (an implant sinker or a trench sinker) within the source contact to connect the top source to the P+ substrate resulting in a large cell pitch due to the dimensions occupied by the sinker region, or on the outside of the cell resulting in higher source resistance. G. Cao et al. in “Comparative Study of Drift Region Designs in RF LDMOSFETs”, IEEE Electron Devices, August 2004, pp 1296-1303, disclose a bottom source lateral LDMOS device, as shown in FIG. 1A, includes a deep sinker diffused within the source contact.
Ishiwaka O et al. disclose in “A 2.45 GHz power Ld-MOFSET with reduced source inductance by V-groove connections”, International Electron Devices Meeting—Technical Digest, Washington, D.C., USA, 1-4 Dec. 1985, pp. 166-169, discloses a lateral double-diffused MOS field effect transistor (LD-MOSFET) with V-grooved source connections employed to minimize the source inductance, the gate-to-drain capacitance and the channel length. The V-grooves, which penetrate the P− type epitaxial layer and reach the P+ type substrate, are formed in the SiO2 region just outside the active area. The N+ type source regions of the LD-MOSFET are directly connected to the V-grooves with metallization, thus eliminate the bonding wires for the source.
In U.S. Pat. No. 6,372,557 (Leong, Apr. 16, 2002), which discloses a bottom source lateral LDMOS device, attempts are made to use a buried layer at the interface of the P+ and P-epitaxial layers to reduce the lateral diffusion and hence reduce cell pitch. U.S. Pat. No. 5,821,144 (D'Anna et al., Oct. 13, 1998) and U.S. Pat. No. 5,869,875 (Hébert, Feb. 9, 1999) also disclose lateral DMOS devices that include a deep sinker region (an implant sinker or a trench sinker) on the OUTER periphery of the structure to reduce the cell pitch.
However, in these disclosures, the devices use a single metal over the source/body contact regions and gate shield regions, which is thick (3 um or more) then due to its thickness it will have higher capacitance from the source metal to N-drift drain, more stress on the gate and also larger spacing to drain metal, thus increases the cell pitch. In the other hand, some of the devices use a first metal for the source/body contact regions and a second metal for drain and gate shield regions, then the first metal is thinner so it can wrap around the gate and shield it with lower capacitance and less stress and does not affect the cell pitch. However, using two metals adds cost since it needs two extra masks—one for via and the other for top metal. These configurations generally form the P+ sinker through top down diffusion resulting in large cell pitch due to the significant lateral diffusions of the deep sinker used to connect the top source down to the highly doped substrate, which increases the overall size of the cell over the horizontal plane. A large cell pitch causes a large on-resistance that is a function of resistance and device areas. A large cell pitch also increases the device costs due to a larger size of the device and a larger size package. Furthermore, reducing the cell pitch of these prior art bottom-source devices results in shifts in the electrical performance of the device. For example, bringing the diffused sinker (which is p+ in doping) closer to the source side of the gate in FIG. 1A will result in a higher threshold voltage since the lateral diffusion of the diffused p+ sinker used to connect the top source to the bottom substrate will encroach in the channel region under the gate, which is also p-type, increase the doping concentration in the channel and hence, increase the threshold voltage, which is an undesirable result.
U.S. Pat. No. 7,554,154 discloses an improved inverted ground-source FET on highly doped substrate, e.g., highly doped P+ substrate, as shown in FIG. 1B, with a self-aligned body-source contact for a reduced cell pitch. The improved FET includes an integrated body-source short structure, i.e., the P+ sinker, which diffuses at the lower portion under the channel and toward the drain. The P+ sinker extends under surface channel to compensate drain extension doping, thus lower Cgd and reduce the cell pitch. In addition, the dopant concentration of the accumulation region is fine tuned to minimize Cgd*Rdson figure of merit. With this top drain LDMOS structure, a buried gate shield is implemented for body-source contact and to reduce the gate to drain capacitance Cgd and the device cells are arranged in a closed configuration that can further reduce extra space required for termination. However, significant lateral diffusions of the deep P+ sinker used to connect the top source down to the highly doped substrate occupies greater space thus limiting further reduction and shrinking of the cell pitches.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new device configurations and manufacturing method in forming the power devices such that the above discussed problems and limitations can be resolved.